RISC-V
risc-v-41dee847·2 events·first seen 1mo agoAliases: RISC-V
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Meta Announces Four MTIA AI Chip Generations in Two Years: MTIA 300–500 Roadmap
Meta has detailed a rapid four-generation MTIA chip roadmap (300, 400, 450, 500) developed in partnership with Broadcom, spanning ranking/recommendation inference and training through general GenAI workloads. Key advances include a 4.5x HBM bandwidth increase and 25x compute FLOPS improvement from MTIA 300 to 500, with MTIA 450 and 500 targeting GenAI inference with doubled and further-increased HBM bandwidth versus leading commercial products. MTIA 300 is in production for R&R training, MTIA 400 is lab-tested and entering deployment, while MTIA 450 and 500 are scheduled for mass deployment in early 2027 and 2027 respectively. The strategy emphasizes modular chiplet design and short iteration cycles to keep hardware aligned with rapidly evolving AI model requirements.
Nvidia's AI Systems Design Chip Circuits, Verify Designs, and Test New Layouts
Nvidia chief scientist Bill Dally described the company's use of AI across five stages of chip design at GTC 2025, including NVCell (a RL+genetic algorithm system that redesigns ~2,500-3,000 layout cells overnight vs. 10 engineer-months), PrefixRL (RL-designed arithmetic circuits 20-30% better than human designs), and ChipNeMo/BugNeMo (LLaMA 2-based LLMs fine-tuned on internal GPU documentation). The systems demonstrate measurable improvements over human and industry-standard designs, though Dally acknowledged that fully autonomous GPU design from a prompt remains a distant goal. The piece also references a 2025 Verkoran paper describing an agentic system that autonomously designed a RISC-V CPU from a 219-word specification.